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Figure 5.22 shows the phase distribution for = 1 and different values of A. The pdf of the power is given as pdfP (P ) = 1 + Kr exp Kr (Kr + 1)P I0 2 Kr (Kr + 1)P for P 0 (5.34)
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[Lue84a] R. J. Luebbers, Finite conductivity uniform GTD versus knife edge diffraction in prediction of propagation path loss, IEEE Trans, Antennas Propag., AP-32, 70 76 (1984). [Lue84b] R. J. Luebbers, Propagation prediction for hilly terrain using GTD wedge diffraction, IEEE Trans. Antennas Propag., AP-32, 951 955 (1984). [Lyo75] D. L. Lyon, Envelope-driven timing recovery in QAM and SQAM systems, IEEE Trans. Commun., COM-23, 1327 1331 (1975). [Mac77] F. J. MacWilliams and N. J. A. Sloane, The Theory of Error-Correcting Codes, NorthHolland, Amsterdam, 1977. [Mag73] R. F. Magee and J. G. Proakis, Adaptive maximum likelihood sequence estimation for digital signaling in the presence of ISI, IEEE Trans. Inf. Theory, IT-19, 120 124 (1973). [Man00] D. Manolakis, V. Ingle, and S. Kogon, Statistical and Adaptive Signal Processing, McGraw-Hill, New York, 2000. [Mar85] M. J. Marcus, Recent U.S. regulatory decisions on civil use of spread spectrum, Proc. IEEE GLOBECOM 85, New Orleans, LA, Dec. 1985, pp. 16.6.1 16.6.3. [Mar87a] M. J. Marcus, Regulatory policy considerations for radio local area networks, IEEE Commun. Mag., 25(7), 95 99 (1987). [Mar87b] S. L. Marple, Digital Spectral Analysis with Applications, Prentice Hall, Englewood Cliffs, NJ, 1987. [Maz75] J. E. Mazo, Optimum timing phase for an in nite equalizer, Bell Syst. Tech. J., 54, 189 201 (1975). [MBO04] MBOA Physical Layer Technical Speci cation, May 2004. [McG02] J. McGeough, Wireless location positioning, based on signal propagation Data, White Paper, http://www.wirelessdevnet.com/software/, 2002. [McK91] J. W. McKown and R. L. Hamilton, Jr., Ray tracing as a design tool for radio networks, IEEE Network Mag., 5(6), 27 30 (1991). [McL88] P. J. McLane et al., PSK and DPSK trellis codes for fast fading, shadowed mobile satellite communication channels, IEEE Trans. Commun., COM-36, 1242 1246 (1988). [Med83] J. S. Meditch and C. T. Lea, Stability and optimization of the CSMA and CSMA/CD channels, IEEE Trans. Commun., COM-31, 763 774 (1983). [Med93] J. Meditz, Development of custom coded blocks in signal processing workstation (SPW) software for indoor radio propagation modeling, M.S. thesis, ECE Department, Worcester Polytechnic Institute, Worcester, MA, May 1993. [Meh97] A. Mehrota, GSM System Engineering, Artech House, Norwood, MA, 1997. [Met76a] J. J. Metzner, On improving utilization in ALOHA networks, IEEE Trans. Commun., COM-24, 447 448 (1976). [Met76b] R. Metcalfe and D. Boggs, ETHERNET: distributed packet switching for local computer networks, Commun. ACM, 19, 395 404 (1976). [Mic85] A. M. Michelson and A. H. Levesque, Error-Control Techniques for Digital Communication, Wiley-Interscience, New York, 1985. [Mil92] L. B. Milstein et al., On the feasibility of a CDMA overlay for personal communications networks, IEEE J. Sel. Areas Commun., SAC-10, 655 668 (1992). [Mil98] C. Miller and J. Lee, BER expressions for differentially detected /4-DQPSK modulation, IEEE Trans. Commun., COM-46, 71 81 (1998). [Mis02] P. Misra and P. Enge, Global Positioning System: Signals, Measurements, and Performance, Ganga-Jamuna Press, Lincoln, MA, 2002. [Moh89] M. L. Moher, TCMP-A modulation and coding strategy for Rician fading channels, IEEE J. Sel. Areas Commun., SAC-7, 1347 1355 (1989).
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44: Introduction to Web Services
"* Finally, chemomechanical polishing is performed on the SO1 film to give it
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11.4.2 Nanoscale Logic Gates and Computational Circuits High-yield assembly of crossed NW p-n diodes and cNW-FETs from p-Si and n-GaN materials enables more complex functional electronic circuits, such as logic gates, to be produced. Logic gates are critical blocks of hardware in current computing systems, producing a logic-1 and logic-0 output when the input logic requirements are satis ed. Diodes and transistors represent two basic device elements in logic gates.56 Transistors are more typically used in current computing systems because they can exhibit voltage gain. Diodes do not usually exhibit voltage gain, although they may also be desirable in some cases56; for example, the circuit architecture and constraints on the assembly of nanoelectronics might be simpli ed using diodes because they are twoterminal devices, in contrast to three-terminal transistors. In addition, by combining diodes and transistors in logic circuits, it is possible to achieve high voltage gain, while maintaining a simpli ed device architecture. Importantly, the exibility of bottom-up assembly readily allows integration of diode- and FET-based logic.57 For example, a two-input logic OR gate was realized using a 2(p) by 1(n) crossed NW p-n diode array.44 When either of the inputs to the p-NW is high, a high output is obtained at the n-NW as the p-n diode is forward biased; a low output is only achieved when both inputs are low, thus realizing the same function as a conventional logic OR gate (Fig. 11.8a and b). A logic AND gate was also assembled from two p-n diodes and one cNW-FET (Fig. 11.8c and d), and a logic NOR gate with a gain over 5 was assembled from three cNW-FETs in series (Fig. 11.8e and f). Importantly, logic OR, AND, and NOR gates form a complete set of logic elements and enable the organization of virtually any logic circuits. For example, NW logic gates have been interconnected to form an XOR gate and a logic half adder, which were used to carry out digital computations in a way similar to conventional electronics (Fig. 11.8g and h).
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