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The second use of the Edit Component button is to begin or finish editing a part that is already in an assembly. When you are editing a part in the context of an assembly, the title bar of the SolidWorks window reflects the fact that you are editing a part in an assembly, the toolbar changes to a part-editing toolbar, and the lower-right corner of the taskbar displays the words Editing Part, as shown in Figure 16.4.
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See 19 for more information on watching video through Windows Media Player on Vista.
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Is the bypass capacitor very easy to deal with, and therefore, not worth mentioning Statistics indicates that a very high percentage of failure rates in the testing of an RF circuit block is due to inappropriate selection of the bypass capacitor. Obviously, the task of selecting a bypass capacitor or zero capacitor is underestimated. In the testing stage, the bypass capacitor is an indispensable part not only for RF but also for digital circuit blocks. An improper bypass capacitor always leads to ridiculous test results and sometimes, the tested circuit block is simply out of work even though the circuit block has demonstrated excellent performance in the simulation. Blind Selection of Bypass Capacitor Here is a true story: In a famous institute engaging in R&D for a wireless electronic product, an electrical engineer was about to test an RF block circuitry. He was aware that he had to attach a bypass capacitor at the DC power supply port. He asked his supervisor: Which value of capacitor must be selected from the engineering stock room Without any hesitation, his boss answered his question with brimming con dence: 0.01 F ! From then on, the majority of the electrical engineers would apply a 0.01 F capacitor as a bypass capacitor in whatever circuit they designed. Some people had different opinions: The bypass capacitor must be different for various circuits. You can choose the bypass capacitor when you are going to adjust your circuit block into an optimum state by testing. For example, if you are designing a LNA, you may swap out bypass capacitors one by one until you get a maximum of gain or a minimum of noise gure, or until you get both simultaneously. This sounds a pretty good idea, but in reality, it starts to look like little more than a dream. The performance of the LNA might be unchanged even with many different values of bypass capacitors. An easy but lazy way to solve the selection problem for a bypass capacitor is to put a huge crowd of capacitors on the DC power supply port, by which the AC signal should be short-circuited over a very wide frequency range. This method is time-effective and universal, dealing with all the half ground points in the circuit, regardless of the operating frequencies in the circuit block. For example, Figure 14.3 shows a circuit block in which the main operating frequency in the circuit block is 2.4 GHz. A huge crowd of capacitors with values ranging from very low, 10 pF, to very high, 100 F, are connected between the DC power supply port and ground in parallel. The capacitors from C1 to C6 are chip capacitors, while the capacitors from C7 to C12 are electrolytic. The designer thought that, with such a setup, there should be no problem in reaching the goal of AC short-circuiting and DC open-circuiting at DC power supply port. Unfortunately, the huge crowd of capacitors is useless because the AC signal appearing on the DC power supply port is maintained at the same level whether they are connected to or removed from the DC power supply port. This inconceivable event frustrated the designer for a long time. The answer to this problem can be found in Table 14.A.1, where the zero capacitor is discussed: The SRF (Self-Resonant Frequency) of any capacitor in the huge crowd of capacitors is below the operating frequency of 2.4 GHz. From Table 14.A.1 it can be found that the correct value of the bypass capacitor must be 5.1 pF.
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The ninth block in the last column is the back end of the receiver and is excluded and constructed in the base-band portion. The values of performance in the ninth block are provided by the base band designer. There are three portions in Table 18.7: 1) System goals: General goals for all the blocks which are not involved in the calculation. 2) Performance: The expected goals of performance for each individual block are listed, such as gain, NF, IP3 3) Calculation: Calculations are only conducted in this portion on the basis of the expected goals in the performance portion. In the process of calculation, the calculated results are registered in the corresponding cells in this portion. Instead of simultaneously doing the calculations for all the blocks, the calculations are con ned to only two blocks at a time. In other words, only cascaded equations for two blocks are applied in the calculations in Table 18.7. In order to show the calculation path, let s take the calculation of the noise gure as an example. In Table 18.7, the NF values of every block in the Performance portion and the NFsys values of every block in the Calculation portion are circled with an ellipse. The NF values of each block in the Performance portion are the respective expected goals of each individual block and the NFsys values of each block in the Calculation portion is a systematic value of noise gure looking from the block toward all the following blocks in the right hand side. These values are grouped and named group A, B, C, D, E, F, G, and H. The calculation path for noise gure is also shown in Table 18.7. Now calculation is started from group A in the last two blocks. The original noise gure of the back end block, NFsys, shown in the calculation portion is 7 dB, which is provided by the base band circuit designer. The noise gure of SP ampli er, NF, is 0 dB. The new NFsys is the original noise gure of the back end block, NFsys, cascaded with the noise gure of SP ampli er, NF. In terms of the cascaded equation for two blocks, the new or resultant noise gure NFsys can be calculated and is obtained as 7 dB, which is registered into the NFsys cell of the SP ampli er located in the calculation portion. Following a similar calculation path, the calculation moves from group A to B, and then from B to C, from C to D, from D to E, and so on. At last, the nal value of NFsys appears in group H. This value is calculated and is obtained as 5.8 dB. This is the value of the system NF for the entire receiver. By a similar calculation path as shown for the noise gure above, other parameters, such as gain, intercept point, etc. can be calculated starting from the last block and working toward the rst block. All the values located in the column of the rst block in Table 18.7, the HF/Balun, are the entire system values for the receiver. In Table 18.7, not only the gain, noise gure, and intercept point, but also other parameters, such as the 12 dB SINAD, 20 dB quieting, and IMR are presented. It should be noted that in Table 18.7 there are two rows which present the worstcase gain and noise gures, in which the worst case factor is 0.1 = 10%. The purpose of system analysis using the worst case is to retain the necessary room for the high performance reliability of the system.
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