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CHAPTER
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which is a decimal 1. For the assignment of output2 = output1, which is a blocking statement, this statement assignment only occurs after output1 = input1 and output3 = output2 have occurred. Therefore, output2 is assigned the value of decimal 1. Referring to the simulation waveform in Figure 4.16: 1. The Verilog code in Example 4.14 uses a synchronous reset. Therefore, when reset is at logical 1, output1, output2, and output3 are not reset to value of 0 because a positive edge of clock did not occur. 2. On the rising edge of the rst clock, output2 is assigned the value of output1, which is X. Output3 is assigned the value of output2. At the moment when the assignment of output3 = output2 occurs, output2 is at X. Therefore, output3 is also assigned X. For the assignment of output1 = input1, because input1 has a value of decimal 1, output1 is also assigned the value of decimal 1. 3. On the rising edge of the second clock, output2 is assigned value of output1, which is a decimal 1. Output3 is assigned the value of output2, which is a decimal 1. For the assignment of output1 = input1, because input1 has a value of decimal 2, output1 is assigned the value of decimal 2. Referring to simulation waveforms of Examples 4.12, 4.13, and 4.14 (Figs. 4.14, 4.15, and 4.16), it is obvious that use of a blocking statement within an always @ (posedge block gives different simulation results when the order of statement assignment is changed. In other words, use of a blocking statement is order dependent. Referring to simulation waveforms of Examples 4.8, 4.9, and 4.10 (Figs. 4.11, 4.12, and 4.13), use of a nonblocking statement within an always @ (posedge block gives the same simulation results when the order of statement assignment is changed. In other words, use of a nonblocking statement is not order dependent. From the exercise of Examples 4.8 to 4.15, it is concluded that nonblocking statements must be used when coding for registers. When coding for combinational logic, blocking statements are used. This ensures that when a designer is writing code to synthesize registers, the order in which the nonblocking statements are written will not affect simulation. Note: When writing Verilog code that involves more than one register assignment, always use nonblocking statements. This will ensure that the order in which the register assignments is made does not affect the simulation results.
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If you use the right chocolate, at the right time, it can have very healthful properties. A 1/2 oz (14 g) serving of milk chocolate has 75 calories and 8 milligrams of caffeine. Dark semi-sweet chocolate has only 30 calories and 8 milligrams of caffeine in a 1/2 oz. Dark semi-sweet chocolate contains cocoa butter, which is like olive oil. Cocoa butter does not raise cholesterol and has a beneficial effect on blood lipid profile. Milk chocolate contains butter fat, which raises cholesterol
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Fig. 7.6
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